1. Field of the Invention
This invention relates to a data processing circuit for use in a digital audio system such as a digital audio disc (DAD) player.
2. Prior Art
For correcting data errors in a digital audio disc, there has recently been used a CIRC (Cross Interleave Reed Solomon Code) method. With this method, musical signal data read from the disc in a digital audio disc player are once stored in an associated memory, and then the data are read from this memory, checked, corrected if the data contain any error, and fed to DAC (digital- to-analog converter) through associated circuits. This invention relates to a data processing circuit for performing the above-described data processing of the musical signal data with simplified hardware.
A digital audio disc player in which the data error is detected with the CIRC method will now be described. This data error detection method is already known in the art and is described in Japanese Patent Application Laid-Open (Kokai) No. 57-4629.
FIGS. 1 and 2 diagrammatically show a write circuit for writing data into the disc and a data processing circuit for processing the data read from the disc, respectively. In FIG. 1, reference characters L6n, R6n ------ R6n+5 each designates musical signal data composed of 16 bits, and each musical signal data is composed of two symbols each having 8 bits. For example, the musical signal data L6n is composed of two symbols W12n,A and W12n,B. The total of 24 musical signal symbols W12n,A to W12n+ll,B of the musical signal data L6n to R6n+5 are selectively delayed by two units of delay time at delay portion Dly1 and then the order of them are changed at cross portion Cr1. Then parity symbols Q12n to Q12n+3 for error detection based on a Reed Solomon Code method are added to the musical signal symbols at parity circuit Pal so that the total of the symbols is 28, each parity symbol having 8 bits. The 28 symbols are again delayed at delay portion Dly2 (Interleave). In this delay portion Dly2, "D" designates 4 units of delay time (FIG. 1). Then, 4 error correction parity symbols P12n to P12n+3 based on the Reed Solomon Code method are added to the symbols at parity circuit Pa2 so that the total of the symbols is 32, each parity symbol having 8 bits. The 32 symbols are selectively delayed by one unit of delay time at delay portion Dly3. Then, complementary data of the parity symbols P and Q are outputted from inverters shown in the figure. Thus, data DWD to be recorded on the disc are formed. The data DWD are sequentially modulated in an EFM (Eight to Fourteen Modulation) manner from the top symbol (FIG. 1) and are written into the disc.
FIG. 3 schematically shows a format of the data as recorded on the disc, the data comprising a number of frames Fr each of which includes a synchronization pattern SYNC added to the data to be recorded on the disc, symbols W0 to W23 corresponding to the musical data, and error correction parity symbols Q0 to Q3 and P0 to P3. The frame Fr is a data unit for data error correction. When a symbol is be delayed by one unit of delay time, the symbol is written into a frame Fr next to the frame Fr into which the symbol would otherwise be written if it were not delayed.
Next, for reproducing the data, the data read from the disc are demodulated by an EFM demodulation circuit and changed into the data DWD, i.e., the data as they were before being written into the disc. Each symbol of the data DWD is first selectively delayed by one unit of delay time by delay portion Dly4 (FIG. 2), so that the delay of symbol effected by delay portion Dly3 (FIG. 1) is corrected. Then, the error correction parity symbols P and Q are fed to C1 decode circuit C1dec via inverters while the other symbols are fed directly to C1 decode circuit C1dec. C1 decode circuit C1dec calculates syndromes in accordance with each symbol, and detects incorrect symbols with the Reed Solomon Code method, using the syndromes so calculated (error detection based on parity symbols P), and corrects the data errors. Each symbol outputted from C1 decode circuit C1dec is delayed by delay portion Dly5, so that the delay of the symbols effected by delay portion Dly2 (FIG. 1) is corrected, and fed to C2 decode circuit C2dec. C2 decode circuit C2dec detects and corrects the errors (error detection based on parity symbols Q) in the symbols in the same manner as C1 decode circuit C1dec does. The order of the symbols outputted from the C2 decode circuit C2dec is changed by cross portion Cr 2, so that the order of the symbols changed by cross portion Cr 1 is restored. Then, the symbols are selectively delayed by delay portion Dly6 by a time period corresponding to two symbols, so that the delay of the symbols effected by the delay portion Dly1 (FIG. 1) is corrected to obtain the original musical signal data L6n to R6n+5 again. These musical signal data are sequentially fed to DAC in which they are converted into analog signals, and then these signals are applied to a loudspeaker to produce musical sounds.
The data processing including data error correction with the CIRC method in the digital audio system is performed as described above. A memory for storing the symbols (symbol memory) is not shown in FIGS. 1 and 2. Actually, however, the symbols read out from the disc are once stored in the memory and then these symbols are read from this memory and subjected to the processing in FIG. 2, including the delay processing. Thus, it is necessary for a data processing circuit of a digital audio system to control the writing into memory of the musical data read from the disc and the addressing of the memory in a complicated manner.